In the manufacture of highly dense semiconductor memory devices, a greater number of storage cells are coupled together along a single conductive line. This conductive line (i.e., word line) typically forms the control electrode of at least one of the devices that comprise a given memory cell. For example, in the so called one-device dynamic random access memory cell comprising a transistor coupled to a storage capacitor, the word line provides the gate electrode of the transistor.
It is known in the art to reduce the sheet resistance of word lines by utilizing low resistance conductors such as aluminum. Back in the early to mid 1970's those materials were widely accepted throughout the industry. However, the development of the self-aligned FET (in which the source and drain impurity regions are implanted into regions of the substrate partially defined by the gate electrode) necessitated the adoption of heat-resistant conductors such as polysilicon.
Another method of reducing sheet resistance is to use refractory metal silicides that are formed on top of (i.e., "strap") a polysilicon gate. Typically, as shown in U.S. Pat. No. 4,593,454 (issued June 10, 1986 to Baudrant et al), a silicide layer is formed simultaneously over the gate electrode and the source/drain difusion regions of an FET device. More specifically, after a polysilicon gate electrode has been defined on a substrate, ions are implanted to define the source/drain diffusion regions. Then an oxide layer is deposited and etched so that the sidewalls of the polysilicon gate electrode are covered with oxide. Then a refractory metal layer (the patent utilizes tantalum) is deposited on the substrate, and a heat cycle is carried out to form tantalum silicide in those portions of the tantalum disposed on exposed silicon. Note that the oxide disposed on the sidewalls of the polysilicon gate electrode prevent the silicide formed on the upper surface of the gate electrode from being connected to the silicide formed on the source/drain regions.
The general simultaneous gate and source/drain silicide formation process as exemplified by the Baudrant et al patent suffers from several shortcomings. A recent trend in the semiconductor industry is to decrease the depth of the source/drain diffusion regions to less than 0.5 microns. These so-called "shallow junctions" are more resistant to punchthrough defects as the channel length of FET's is decreased below the one micron barrier. If a refractory metal is deposited over the shallow junctions to form a silicide thereon, the amount of junction silicon consumed during the silicide reaction may substantially degrade the characteristics of these shallow junction regions. In the prior art, this problem has been addressed by incorporating extra silicon at the shallow junction surface prior to refractory metal deposition. For example, as shown in an article by Reith et al, entitled "Controlled Ohmic Contact and Planarization For Very Shallow Junction Structures," IBM Technical Disclosure Bulletin, Vol. 20, No. 9, Feb. 1979, pp. 3480-3482, after implantation epitaxial silicon is grown so as to maintain the integrity of the shallow junctions after silicide formation. This process presents a tradeoff. By decreasing the silicon consumption of the source/drain regions by selective epi growth, the high temperature inherent in this process will drive the source/drain dopants further into the substrate, thus degrading the desired shallow junction characteristics.
In U.S. Pat. No. 4,587,718 (issued May 13, 1986 to Haken et al) the gate electrode silicide is formed prior to the source/drain silicides. A nitride mask is used to define a polysilicon gate electrode atop an oxide layer that completely covers the device area. The source/drain diffusion regions are then formed by implantation through this oxide layer, using the nitride/poly stack as an implantation mask. The nitride mask is then removed, and a layer of refractory metal is deposited on the substrate. The refractory metal layer (in this case titanium) will react with the exposed polysilicon gate without forming a silicide over the source/drain regions, because these regions are covered with the silicon oxide layer. After the gate electrode silicide formation process is completed, the oxide layer above the source/drain diffusion regions is removed, and a second layer of titanium is deposited on the substrate. During the course of the subsequent source/drain silicide reaction, the earlier-formed titanium silicide gate electrode will increase in thickness. Thus, a thick titanium silicide layer is formed on the gate electrode, and a thin titanium silicide layer is formed over the source/drain regions.
See also U.S. Pat. No. 4,453,306 (issued June 12, 1984 to Lynch et al). After the gate electrode silicide is formed, the upper surface of the electrode is covered with oxide. Subsequently, polysilicon is deposited on the device, and is patterned so that it overlays only the source/drain regions. Cobalt is then deposited on the device and is sintered to form cobalt silicide electrodes on the source/drain regions. The oxide atop the silicide gate electrode prevents further silicide formation thereon.
The present inventors have investigated various methods of reducing the sheet resistance of the gate electrode below that obtained by refractory metal silicides. Tungsten silicide provides a resistivity of approximately 50 micro ohms-cm. On the other hand, a tungsten layer has a resistivity of approximately 10 micro ohms-cm, and an aluminum layer has a resistivity on the order of 3 micro ohms-cm. Thus, the inventors considered modifying an approach similar to the Lynch et al patent by replacing the silicide gate formation step with depositing either tungsten or aluminum. However, this modification would not achieve the intended result. If tungsten were to be deposited on top of a layer of polysilicon, the layers would react to form a silicide during the subsequent implant drive-in and source/drain silicide formation steps. This would greatly increase the sheet resistance of the gate electrode by forming tungsten silicide (as opposed to pure tungsten). Similarly, the physical/electrical qualities of an aluminum layer (or an aluminum alloy such as aluminum/silicon) would substantially degrade when exposed to these high processing temperatures.
Another potential problem is presented by forming a refractory metal silicide on the gate electrode. Some CMOS circuits utilize so-called "dual work function" gate electrodes. In this technology, the polysilicon gates for the n-channel and p-channel devices are doped with P-type and N-type dopants, respectively, in order to achieve an enhanced p-channel device characteristic. If these differentially-doped polysilicon gate electrodes are covered with a refractory metal layer for subsequent silicide formation, the polysilicon dopants may intermix (due to the high dopant diffusivity in refractory metal silicides) to destroy the above dual-work function advantages.
Accordingly, a need has developed in the art to provide a FET device having a low sheet resistance metal-strapped polysilicon gate electrode as well as silicide source/drain electrodes.